An electronic circuit contains many individual electronic circuit components, e.g., thousands or even millions of individual resistors, capacitors, inductors, diodes, and transistors. These individual circuit components are interconnected to form circuits, and the circuits are interconnected to form functional units. Microelectronic packages, such as chips, modules, circuit cards, circuit boards, and combinations thereof, are used to protect, house, cool, and interconnect circuit components and circuits.
Within a single integrated circuit (IC), circuit component to circuit component and circuit to circuit interconnection, heat dissipation, and mechanical protection are provided by an IC chip. The chip that is enclosed within its module is referred to as the first level of packaging. The first level package can be a dual in-line pin (dip) or quad flat pack, for example.
There is at least one further level of packaging. The second level of packaging is a circuit card. A circuit card performs at least four functions. First, the circuit card is used if the total required circuit or bit count to perform a desired function exceeds the bit count of the first level package, i.e., the chip. Second, the second level package, i.e., the circuit card, provides a site for components that are not readily integrated into the first level package, i.e., the chip or module. These components include, e.g., capacitors, precision resistors, inductors, electromechanical switches, optical couplers, and the like. Third, the circuit card provides for signal interconnection with other circuit elements. Fourth, the second level package provides for thermal management, i.e., heat dissipation.
The industry has moved away from the use of pins as connectors for electronic packaging due to the high cost of fabrication, the unacceptable percentage of failed connections which require rework, the limitations on input/output (I/O) density, and the electrical limitations of the relatively high resistance connectors. Solder balls are superior to pins in all of the above features as well as being surface mountable, which has obvious implications given the increasingly small dimensions in the forefront technologies today.
Solder mounting is not a new technology. The need remains to improve the solder systems and configurations, however, in electronic structures. The use of solder ball connectors has been applied to the mounting of IC chips using the so-called "flip-chip" or controlled collapse chip connection (C4) technology. Many solder structures have been proposed to mount IC chips, as well as to interconnect other levels of circuitry and associated electronic packaging.
Solder typically comprises an alloy of a more nobel metal such as silver (Ag) or lead (Pb) and a more reactive metal such as indium (In) or tin (Sn). The alloy has a lower melting temperature (LMT) than either of the constituent elements. The combination of the elements of the alloy that has the lowest melting temperature is known as the "eutectic alloy." For example, the eutectic Pb/Sn solder alloy is 37/63 weight percent Pb/Sn and has a melting temperature of about 183.degree. C.
Ball grid array (BGA) modules are a type of surface mount module which have an area array of high melting temperature (HMT) solder ball leads. The basic structure is that of a minute solder portion, generally a ball, connected to a bonding site on one of the parts to be electrically joined. The assembly of the part, bonding pad, and solder is then brought into contact with a solderable pad on a second part and the solder is reflowed to achieve the connection. One of the major drawbacks of this configuration is that the solder balls do not always remain in place before connection, during processing, or upon rework. During rework, not only the solderable pad, but also the solder itself, becomes molten. There is no guarantee, therefore, that the solder will remain associated with the first part during heating in subsequent processing.
To handle a large number of I/O's per chip, various BGA and flip chip bonding methods have been developed. In these flip chip bonding methods, the face of the IC chip is bonded to the card.
Flip chip bonding allows the formation of a pattern of solder bumps on the entire face of the chip. In this way, the use of a flip chip package allows full population area arrays of I/O. In the flip chip process, solder bumps are deposited on solder wettable terminals on the chip and matching footprints of solder wettable terminals are provided on the card. The chip is then turned upside down, hence the name "flip chip," the solder bumps on the chip are aligned with the footprints on the substrate, and the chip-to-card joints are all made simultaneously by the reflow of the solder bumps.
The wettable surface contacts on the card are the "footprint" mirror images of the solder balls on the chip I/O's. The footprints are both electrically conductive and solder wettable. The solder wettable surface contacts forming the footprints are formed by either thick film or thin film technology. Solder flow is restricted by the formation of dams around the contacts. The chip is aligned, for example self-aligned, with the card, and then joined to the card by thermal reflow. The assembly of chip and card is then subject to thermal reflow in order to join the chip to the card.
When the packaging process uses organic carriers (e.g., laminates, Teflon.RTM., and flex), the first level flip chip attach process must be performed at low temperature. Although it would seem that a low temperature flip chip would be desirable, this is not the case because the first level interconnection would reflow during subsequent second level attach (assuming a laminate chip carrier). It is well known that the amount of molten solder in this type of flip chip interconnection can cause reliability problems, such as severe delamination.
Flip chips have a grid array of C4 bumps comprising an HMT solder alloy on metal pads on the front side of the chip. The flip chips are positioned on metalized ceramic or organic substrates with the bumps above corresponding metal pads. The assembly is heated to about 20.degree. C. above the solder melting temperature to melt (reflow) the C4 to form solder joints between the corresponding pads of the chip and substrate.
A representation of the general arrangement of an unassembled package 1 is shown in FIG. 1. This package 1 includes an IC chip 10 and a card 21 to be joined by C4 bonding. Solder balls 30 are present on the I/O leads of the IC chip 10. The solder balls 30 on the IC chip 10 correspond to recessed lands on the circuit card 21.
A cutaway view of the assembled microelectronic circuit package 1 is shown in FIG. 2. FIG. 2 shows an IC chip 10 mounted on a circuit card 21. The IC chip 10 is electrically connected and metallurgically bonded to the circuit card 21 by the solder joints 32. FIG. 2 also shows the internal circuitry of the card 21, for example through holes and vias 23, and signal planes and power planes 25.
FIG. 3 is a cutaway view of an IC chip 10 and card 21 with a reflowed solder ball connector 31. This structure is representative of the prior art. The IC chip 10 has an array of I/O leads 11, i.e., contacts 12 on the internal leads 13. The individual contacts 12 are surrounded by a passivation layer 14. Recessed within the passivation layer 14 are ball limiting metallurgy (BLM) wells with an adhesion layer 15, e.g., a chromium (Cr) adhesion layer 15, a wettable metal layer 16, e.g,. a copper (Cu) layer 16, and a flash layer 17, e.g., a gold (Au) flash layer 17. Extending outwardly from the chip 10 is the solder ball 30. The solder ball 30 has a characteristic spherical shape because it has been reflowed. The circuit card 21 has a eutectic Pb/Sn coated on adhesion pad 51.
High melting temperature solder alloys have been used to connect flip chips onto ceramic substrates. Typically, HMT solder alloys include more of the nobel element. For example, a solder alloy of 97/3 weight percent Pb/Sn has a melting temperature of about 330.degree. C. As a means of supporting a solder hierarchy for the subsequent packaging and providing good mechanical fatigue properties of the solder ball, the C4 solder alloy is nominally 97/3 Pb/Sn. The very high Pb content results in a melting point above 300.degree. C. which makes it an unsuitable solder for wetting to the organic laminates.
This technology was originally developed for ceramic chip carriers. Newer chip carriers are polymeric. In order to allow reflow at temperatures that do not damage these polymeric chip carriers, it is desirable to lower the melting temperature of the C4 solder column. This can be done by applying a thin coating of Sn to the Pb/Sn alloy. The Sn diffuses into the solder column, thereby locally lowering the melting temperature. U.S. Pat. No. 5,075,965 issued to Carey et al., and incorporated herein by reference, discloses a process in which Sn is evaporated through a mask onto the Pb/Sn alloy solder column to form an Sn cap in the shape of a truncated cone. Other methods of applying Sn include evaporated Sn on C4 (known as solder-on-chip or SOC), "tin capping" in which wafers are loaded into the solder evaporation equipment a second time to have a thin film of pure Sn deposited on the top of the C4, and eutectic tin-lead plating (TLP) on the card or chip carrier. These processes are expensive, however, and add to the cost of fabrication.
Standard organic chip carriers cannot withstand temperatures required for high temperature solders. Within the last few years, various methods of joining high melting point solders to an organic product at temperatures of 250.degree. C. or lower have been used. One method includes plating eutectic Pb/Sn solder on the pads of organic carriers, as in the case of C4 chip joining. Another method includes screening eutectic solder paste on the product. Joining is accomplished by reflowing the eutectic solder while it is in contact with the higher temperature solder, thereby forming an alloyed joint between the two solders. Both the pattern plating and screening processes are labor intensive and expensive.
In the C4 process, as distinguished from the earlier flip chip process, the solder wettable terminals on the chip are surrounded by ball limiting metallurgy (BLM), and the matching footprint of solder wettable terminals on the card are surrounded by glass darns or stop-offs, which are referred to as top surface metallurgy (TSM). These structures act to limit the flow of molten solder during reflow.
The BLM on the chip is typically a circular pad of evaporated, thin films of Cr, Cu, and/or Au. The Cr dam formed by this conductive thin film well restrains the flow of the solder along the chip, seals the chip module, and acts as a conductive contact for the solder. In the prior art, the BLM and solder are deposited by evaporation through a mask to form an array of I/O pads on the wafer surface. The term "mask" is used generically. The mask can be a metal mask. Alternatively, as used herein, the "mask" can refer to a sequence of BLM deposition, photoresist application, development of the photoresist, and deposition of solder, followed by simultaneous removal of the photoresist and subetching of the BLM, with the solder column acting as a mask.
Presently, there are several techniques that are being developed or used to join high temperature solder to laminates. Some of these processes deposit pure Sn in close proximity or in contact with the BLM on the chip. When C4 technology chips are subjected to a tin coating process, the edge of the BLM contacts the Sn. Subsequent thermal processing causes the Sn to dissolve the BLM. Reaction of the Sn with the Cu in the BLM during solder reflow causes the formation of an undesirable Cu/Sn intermetallic. Excessive intermetallic formation results in C4-to-chip electrical problems.
Organic circuit boards are typically either rigid boards of epoxy filled with fiberglass and reinforced with wiring layers on each external side, or flexible laminates of patterned copper films and polyimide films. Solder paste includes LMT solder alloy particles, flux to remove any surface oxidation, and a liquid carrier. Solder paste is screen printed onto metal pads on the organic circuit board. Leads, such as gull wing leads of surface mount components, are positioned on the paste on the pads and the assembly is heated to reflow the solder to form solder joints between the leads and pads.
Although the art of semiconductor chip to supporting substrate connections is well developed, there remain some problems inherent in this technology. One particular problem is the high processing cost of reducing the melting temperature of the C4 solder column by applying a thin coating of Sn to the Pb/Sn alloy. Another problem is that the edge of the BLM comes into contact with the Sn. Therefore, a need exists for a method and structure which increase the reliability of the connection between an area array package and a supporting substrate.